Microchip Technology /ATSAME51J19A /QSPI /CTRLB

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Interpret as CTRLB

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (SPI)MODE 0 (LOOPEN)LOOPEN 0 (WDRBT)WDRBT 0 (SMEMREG)SMEMREG 0 (NORELOAD)CSMODE 0 (8BITS)DATALEN0DLYBCT0DLYCS

CSMODE=NORELOAD, DATALEN=8BITS, MODE=SPI

Description

Control B

Fields

MODE

Serial Memory Mode

0 (SPI): SPI operating mode

1 (MEMORY): Serial Memory operating mode

LOOPEN

Local Loopback Enable

WDRBT

Wait Data Read Before Transfer

SMEMREG

Serial Memory reg

CSMODE

Chip Select Mode

0 (NORELOAD): The chip select is deasserted if TD has not been reloaded before the end of the current transfer.

1 (LASTXFER): The chip select is deasserted when the bit LASTXFER is written at 1 and the character written in TD has been transferred.

2 (SYSTEMATICALLY): The chip select is deasserted systematically after each transfer.

DATALEN

Data Length

0 (8BITS): 8-bits transfer

1 (9BITS): 9 bits transfer

2 (10BITS): 10-bits transfer

3 (11BITS): 11-bits transfer

4 (12BITS): 12-bits transfer

5 (13BITS): 13-bits transfer

6 (14BITS): 14-bits transfer

7 (15BITS): 15-bits transfer

8 (16BITS): 16-bits transfer

DLYBCT

Delay Between Consecutive Transfers

DLYCS

Minimum Inactive CS Delay

Links

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